Paper Title
On The Hardware Implementation of Binarization for High Efficiency Video Coding

This paper proposes a way of making hardware architecture of CABAC (Context Adaptive Binary Arithmetic Coding) binarizer in HEVC (High Efficiency Video Coding) that describes in detail with implementation in Simulink. Binarizer itself consists of a controller module, single format modules, combined format modules and custom format modules. Single format module contains FL (fixed length binarization) module, TR (truncated Rice binarization) module, TU (truncated unary binarization) module, EGK (k-th order exp-Golomb coding) module. Combined format module contains CALR (coeff_abs_level_remaining) module and QP Delta (cu_qp_delta_abs) module. Custom format module contains Intra Pred (intra_chrome_pred_mode) module, Inter Pred(inter_pred_idc) module and Part Mode(part_mode) module. Each module was tested and verified with test vectors. The controller module for the binarizer that combines all the components together and invokes different components depending on the syntax elements. Keywords- Binarizer, CABAC, Hardware, HEVC.