Paper Title
Modified Design of Low-Power High Speed Truncation-Error-Tolerant Adder And Its Application in Digital Signal Processing

In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSIdesign and test, error tolerance (ET), a novel error-tolerant adder (ETA)is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.Thus by modifications, we can reduce power,delay and area.