Paper Title
Enhancing Speed And Reducing Power Of Shift And Add Multiplier

This paper presents a technique to enhance the speed of conventional shift and add multiplier. The shift and add logic occupies very small area compared to other multiplier structures but usually it is slow due to sequential operation. To improve speed, we propose modified shift and add architecture that is capable of processing two bits of multiplier in single clock cycle under certain conditions. This is achieved with little area overhead of 2x1 multiplexers that allows single and two bit shifting of product register. The results show the 65% improvement of speed and 20% reduction in power with only 6.8% increase in area. Hence, the proposed multiplier can be used in low area, low power and moderate speed applications. Index terms- Array multiplier, Booth Multiplier, Shift and add Multiplier, Low area