Paper Title
AUTOMATED TESTBENCH GENERATORSOC INTERCONNECT VERIFICATION

Abstract
In modern complex Systems on Chip (SoCs), verifying the interconnect that links numerous bus initiators and targets presents a major challenge. This process involves validating multiple interface protocols, handling various transaction type conversions, and managing extensive combinational transaction paths. To address these difficulties, Verification Intellectual Property (VIP) components are employed for each protocol, along with a dedicated verification platform for the interconnect. However, manually configuring each VIP to integrate with all initiator and target interfaces is time-consuming and labor-intensive. Additionally, adapting these configurations to frequent specification updates driven by market demands is highly challenging. By utilizing an automated environment powered by aAutomated Testbench Generator (ATG) to create these configurations, the time and effort needed for verifying the SoC backbone interconnect can be significantly reduced. Keywords - Interconnect Bus Matrix Verification, Automated Testbench Generator, Automation.