A COARSE-GRAINED PARALLEL CIRCUIT SIMULATION ALGORITHM FOR LARGE-SCALE MOSFET CIRCUITS

Abstract
This paper discusses the method of using parallel computing for large-scale circuit simulation to derive transient responses. As we know, circuit simulation is a crucial step in IC design, requiring substantial hardware resources and a lot of computing time. The rise of modern parallel hardware has necessitated the efficient utilization of parallel computing in this field. Research in this area has shown that while more efficient algorithms can accelerate simulation, they are often difficult to adapt for parallel computation. On the other hand, simple and less refined algorithms are more suitable for parallel implementation. This creates a dilemma when considering parallel computing: the inability to effectively integrate efficient circuit simulation algorithms well. Our previous attempts to incorporate efficient algorithms into parallel computation using fine-grained approaches yielded unsatisfactory results. Therefore, this paper proposes a novel method that combines the advantages of both efficient algorithms and parallel computing. We are introducing a coarse-grained approach, which we refer to as the "Block-based method." In this approach, the entire circuit is first partitioned into conventional subcircuits like traditional methods. These subcircuits are then further assigned into blocks. Our simulation strategy involves applying highly efficient algorithms within each block for computation and enabling parallel simulation across all blocks. The Blocking-based circuit simulation algorithm has been implemented and compared to various algorithms including ITA (Iterated Timing Analysis), and NR-Direct (Nonlinear Relaxation-based Direct approach). Experiments have been carried out to justify the new algorithm. Table 1 presents our simulation results, while Figures 1 describe tested circuits and Figure 2 display the output waveforms. The results demonstrate that, for most circuits, this block-based method achieves the best simulation performance. Thus, good progress has been made in the designated topic of parallel circuit simulation. Moreover, if implemented on hardware with better scalability, the speedup can be further substantially increased. Keywords - Coarse-Grained Parallel Computation, Circuit Simulation, Relaxation-Based Numerical Algorithms, Multicore CPU, Nonlinear Relaxation