Paper Title
2-Digit BCD Square-Root Architecture Using the Square Root Algorithm

Abstract
Arithmetic Logic Units (ALUs) are very important components in computer systems. They are digital circuits utilized to perform a wide variety of arithmetic and logic operations. Modern Central Processing Units (CPUs) contain powerful and complex ALUs. One such operation performed by ALUs is that of Square-Root, namely Binary Coded Decimal (BCD) Square-Root. Square-Root scales one variable by the power of ½. BCD Square-Root is utilized in many digital signal processing applications. This project involves the design and implementation of a BCD Square-Root Core using the ‘square root by long division method’ which is a digit recurrence algorithm, ‘pencil and paper method’ of performing square root of decimal numbers. The finite state machine with datapath (FSM-D) architectural model was used extensively in the design of the system. It was implemented in VHDL using Xilinx Vivado 19.2, with the target being the Artix 7 FPGA (XC7A35T-ICPG236C). The implemented system was simulated with Isim Simulator. The post-implementation timing and utilization reports revealed the maximum path delay was 8.812ns while hardware utilization was 820 sliced LUT, 880 FF and 24 IOB. Keywords - Arithmetic Logic Unit, Computer Arithmetic, Square-Root, Square-Root Algorithm, Binary Coded Decimal.