Paper Title
FINE-GRAINED PARALLEL RELAXATION-BASED CIRCUIT SIMULATION

Abstract
In this paper, we investigate the issue of performing fine-grained parallel circuit simulation using relaxation-based algorithms. The methodology here is to adopt relaxation-based algorithms into parallel computing versions. Used algorithms involve WR (Waveform Relaxation), NR-Direct (Nonlinear Relaxation-based Direct approach), and ITA (Iterated Timing Analysis). In our research process, firstly, we establish a data structure capable of storing all parallel computing data, including simulated circuits and obtained waveforms. Secondly, using this data structure, we successfully adapt above relaxation-based algorithms into parallel computing versions. Finally, several example MOSFET circuits are simulated by these versions to observe performance. Also, to know multi-core CPU accelerating capability, additional experiments have been performed. Basing on experimental results and some discussions, we raise some improvement suggestions for parallel relaxation-based circuit simulation, in which some had been justified by our previous researches. Keywords - Find-grained parallel computation, Circuit simulation, Relaxation-based numerical algorithms, Multi-core CPU, Nonlinear relaxation