Novel Multi-Precision Floating Point Multiplier Architecture using Mantissa Similarity Investigation (MSI) for Path-Delay Reduction
Floating point multiplication is a very crucial component of many engineering applications such as image processing and video processing. The dynamic range of numbers represented by floating point format arithmetic is very large when compared to that of fixed point numbers of the same bit-width. This paper presents the development of a novel multi-precision floating point multiplier architecture which can be used in data intensive applications, requiring high throughput, variable precision and low delay. The novel multiplier can be configured to operate in single, double, quadruple and octuple precision modes as set out by IEEE-754 standards for floating point numbers. The system is also prepared to maximize throughput and utilizes mantissa similarity investigation to further reduce path delay of the multiplier system.
Keywords - Floating-Point Multiplier; Arithmetic Logic; Arithmetic Logic Unit; Arithmetic Circuits; FPGAs in Arithmetic.