CFA Based Pipelined S-Box for AES Algorithm
The increasing need for protecting data communication in computer networks has led to development of several cryptography algorithms. The Advanced Encryption Standard (AES) is a computer security standard issued by the National Institute of Standards and Technology (NIST) of US government intended for protecting electronic data. The AES cryptography algorithm is used to encrypt/decrypt blocks of 128 bits and is capable of using cipher keys of 128, 196 or 256 bits wide (AES128, AES196, and AES256).
In this paper, CFA based S-Box operation with the help of combinational logic circuits is presented. In addition to this, pipelining concept is introduced and 2 & 4-stage pipelining with CFA method is done. The design has been coded using Verilog HDL. All the results are synthesized and simulated using Xilinx and ModelSim respectively. The results indicate that when number of pipelined stages increases, system performance improves. Further there is a reduction in the gate delay as pipeline stages increases. It is also seen that the area of the device increases with the pipeline stages increases. Latency would be higher for the addition of pipelined registers.
Keywords � AES; CFA; pipelining;LUTs; FPGAs; HDL.