Design And Implementation Of 64 Bit Multiplier By Using Carry Save Adder
In this paper we have shown the design and implementation of 64 bit multiplier by using multi bit flip flop shift register andcarry save adder . In arithmetic operations addition and multiplication are having a major role.When the number of bits increases, the complexity of adder circuits increases and speed performance decreases.Our proposed system uses two 64 bit numbers and multiply to form a 128 bit number, which is for larger applications. Proposed carry save adder based multiplier, On comparing with the carry look ahead adder based 64 bit multiplier, the results showing time (speed)decreased by93.5% approximately and when comparing with the carry select adder based 64 bit multipliertime (speed) decreased up to 88%. The code is written in VHDL and synthesizedthe design in Xilinx ISE 10.1Version and hardware implementation is in Spartan 3E FPGA family.
Keywords- Shift Register, Single Bit Flip Flop, Multi Bit Flip Flop, Carry Look Ahead Adder, Carry Select Adder, Carry Save Adder, VLSI, VHDL, Spartan.