Fast Parallel Reconfigurable Computing Architecture for Multi-Standard Video Decoding
Video processing applications often require high computing capacity but have performance and power constraints, especially in portable devices. General purpose processors can no longer meet the requirements. In this paper, a parallel reconfigurable computing architecture consisting of reconfigurable processing units interconnected by an area-efficient routing is proposed. The hierarchical configuration contexts are proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed architecture targets multiple-standard video processing. The design is able to provide high performance comparable to the fixed function ASICs through deep pipelining and large amount of computing parallelism. The experimental results demonstratethe proposed architecture has great performance and practicability.
Keywords - Reconfigurable Processing, Performance, Power, Parallel, Multiple-Standard Video Processing.