Paper Title
Fast Settling Operational Amplifier with Low Power Consumption

Abstract
This paper presents a design of fast settling CMOS operational amplifier with a view to optimize the power consumption. Central to this approach is to allocate appropriate spacing between poles and zero so an underdamped transient response with minimum settling time can be obtained with less power consumption. Mathematical analysis using device modeling has been done to determine element values for optimum compensation followed by its simulations in triple metal layer n-well CMOS process using 0.5 μ technology. Best simulation results obtained on Tanner tool show 86.2dB gain, 136.6 MHZ Unity gain frequency(ωu), 25 ns Settling time (ts) with 1pf load, 211V/us Slew rate (SR) with 1pf load, and 2.56mW of power dissipation.