A PCM Receiver for Decoding the Deviated Clock Frequency Data using FPGA Based Embedded System
PCM decommutator is an essential subsystem in any communication system to decode the received parameters. In this work, A full PCM receiver is presented. The proposed PCM receiver is designed utilizing FPGA-based embedded system through USB-UART interfacing. The designed hardware consists of four major parts; a PCM frequency detector, decommutator, shift register and USB-UART interface. The shift register is designed to save the whole decommutated frame until sending it to a PC. The USB-UART interface is designed to enable the communication between the FPGA and the PC USB port. The proposed PCM receiver utilizes each coming pulse to update the sampling frequency to overcome the transmitter clock frequency drift. For the sake of system validation, a PCM transmitter is implemented on another FPGA board for sending clock deviated data to the proposed receiver. Moreover, a monitoring program is implemented on a PC to receive and process the decoded data.
Keywords - PCM decommutator, FPGA-based embedded systems, Digital signal processing & Clock frequency deviation