Paper Title
Block-Level Power Gating MRAM with 96.5% Leakage Reduction

Abstract
This paper exploits circuit techniques to realize a power-gated MRAM with the instant-on characteristic. Each block in a large-capacity MRAM is gated by a separate power transistor, allowing it to be fully turned on after only 1.3 ns. The whole MRAM memory can always be put in sleep mode, except the selected block. This eliminates the need for access pattern prediction as well as the requirement that the MRAM must be in idle for a significant of time before it is put in sleep or deep sleep mode. Our simulation shows that even in the worst-case-scenario, 86% of leakage current is saved. Our proposed scheme’s implementation is straight forward and incurs less than 0.5% area overhead, including power transistors and control circuits. Index Terms - MRAM, low-power, low-leakage, normally-off system