FPGA Implementation Of A Customized Processor Based On Risc-V Architecture – Concept And Theory Of Operation
Various real-time time systems, used in fields like automotive, robotics, or industry, are critical in the true sense of the word. For these systems, the time required to switch task contexts and the real-time operating system jitter introduced in treating aperiodic external events are very important parameters. The present paper describes the implementation of the nMPRA concept (Multi Pipeline Register Architecture - n degree of multiplication) based on the RISC-V architecture. The main characteristic of the nMPRA processor is ensuring the deterministic and performance control of a process. The implementation of the nMPRA architecture provides superior performance in terms of response time to external events and the time needed to switch task contexts; the architecture is suitable for real-time small-scale applications due to the resource consumption required to multiply the multiplexed storage elements. The nMPRA processor is a deterministic hardware implementation, due to the integrated preemptive scheduler and ZScale – RISC-V architecture.
Keywords - Pipeline Processor, Real-time Operating System, Real-time System, Scheduler.