WORLD RESEARCH LIBRARY

Discover, Learn, Share

Paper Detail

FPGA Implementation For Real Time Sobel Edge Detector Block Using 3-Line Buffers
Page(s): 58-63  
Author Ronnie O. Serfa Juan, Chan Su Park, Hi Seok Kim, Hyeong Woo Cha  
Quick Abstract  Add To Library PDF  
WRL Cited By- 261