Paper Title
Image Histogram Equalizer Hardware Implementation Using High Level Sytheisis

Abstract
In this paper, a histogram equalization algorithm is improved by a high level synthesis (HLS) for future implementation in reconfigurable hardware. The aim of this study is to implement histogram equalizer hardware by using Vivado HLS for a real-time processing system on a Field Programmable Gate Array (FPGA). The histogram equalization algorithm is implemented and tested using a colored image which sizes 1600x1200 pixels. Index Terms— Histogram, Histogram Equalization, High Level Synthesis, Image Enhancement