FPGA Implementation For Real Time Sobel Edge Detector Block Using 3-Line Buffers
In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is a model using Finite State Machine which executes a matrix mask operation to determine the level of edge intensity through different pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. The proposed edge detector shows good performance of edge detection with the following results; resource of utilization, obtained a 238.687 MHz on maximum clock frequency, and using MATLAB software; it shows better PSNR results in terms of 3-Line buffers utilization.
Index Terms—FPGA, Sobel Edge Detector, Sobel Mask, 3-Line Buffer