The Implementation of a Pipelined Floating-point CORDIC Coprocessor on NIOS II Soft Processor

This paper discusses the implementation of a pipelined floating-point Coordinate Rotation Digital Computer (CORDIC) coprocessor using Field Programmable Gate Array (FPGA) to accelerate the computation speed in solving elementary functions on NIOS II soft processor. Examples of the elementary functions are trigonometry and hyperbolic functions, exponential, natural logarithm, square root as well as multiplication and division. In order to enhance its functionality, an argument reduction algorithm was introduced to expand the convergence limit for the inputs. The design was developed using a pipelined architecture with 29 stages. In this project, the proposed CORDIC coprocessor was designed as a custom hardware component with Avalon Memory Mapped (Avalon-MM) interface. A dedicated NIOS II system was developed using hardware/software co-design methodology to allow the hardware execution on NIOS II software. Thus, the floating-point data are represented in the 32-bit single precision floating-point format that are compliant with IEEE-754 standard. The design was modelled using System Verilog HDL coding style. The verification was done by comparing the results from the CORDIC hardware and C software using math library. The performance analysis was done to obtain the speedup achieved by the proposed hardware from the corresponding software functions. Finally, the proposed coprocessor was run on Altera DE0 board with a clock frequency of 50MHz. The results achieved precision up to six decimal places, with more than 100 times of speedup against software execution time for most of the elementary functions. However, smaller speedup was achieved for the square-root, multiplication and division operations. Keywords- CORDIC Coprocessor, Elementary Functions, Argument Reduction Algorithm, NIOS II, Avalon-MM Interface