Compression of FPGA Bitstreams Using A Novel Bitmask And RLE Algorithm
The configuration file size of a field-programmable gate array (FPGA) has increased rapidly. Thus, compression techniques are used to decrease the size of bitstreams. Two parameters are employed to measure compression, namely, compression ratio (CR) and decompression speed. Existing studies in this field have focused on two directions: small CR with slow decompression speed, and fast decompression speed at the cost of CR. This paper proposes a novel decode-aware compression technique with small compression ratio and minimal decompression time. The paper contributes to the literature by 1) proposing a novel dictionary selection algorithm that can avoid dictionary repetition, and 2) introducing an improved parameter selection that can provide a better CR. The experimental results showed that our approach outperforms the existing compression maximum of 15% in terms of compression ratio. Moreover, the decompression hardware can operate at 330 MHZ on a Virtex-5 FPGA.
Keyword- FPGA, Bitstream, Compression, Dictionary Compression